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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
February 2000
NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
General Description
The NM24C08/09 devices are 8192 bits of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the Standard IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements. The upper half (upper 4Kbit) of the memory of the NM24C09 can be write protected by connecting the WP pin to VCC. This section of memory then becomes unalterable unless WP is switched to VSS. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s). The Standard IIC protocol allows for a maximum of 16K of EEPROM memory which is supported by the Fairchild family in 2K, 4K, 8K, and 16K devices, allowing the user to configure the memory as the application requires with any combination of EEPROMs. In order to implement higher EEPROM memory densities on the IIC bus, the Extended IIC protocol must be used. (Refer to the NM24C32 or NM24C65 datasheets for more information.) Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption.
Features
I Extended operating voltage 2.7V - 5.5V I 400 KHz clock frequency (F) at 2.7V - 5.5V I 200A active current typical 10A standby current typical 1A standby current typical (L) 0.1A standby current typical (LZ) I IIC compatible interface - Provides bi-directional data transfer protocol I Schmitt trigger inputs I Sixteen byte page write mode - Minimizes total write time per byte I Self timed write cycle Typical write cycle time of 6ms I Hardware Write Protect for upper half (NM24C09 only) I Endurance: 1,000,000 data changes I Data retention greater than 40 years I Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP I Available in three temperature ranges - Commercial: 0 to +70C - Extended (E): -40 to +85C - Automotive (V): -40 to +125C
Block Diagram
VCC VSS WP H.V. GENERATION TIMING &CONTROL START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR E2PROM ARRAY
SDA
SCL
XDEC
A2
WORD ADDRESS COUNTER
R/W
YDEC
CK DIN DATA REGISTER DOUT
DS500071-1
(c) 1998 Fairchild Semiconductor Corporation NM24C08/09 Rev. G
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Connection Diagrams
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
NC NC A2 VSS 1 2 8 7 VCC NC SCL SDA
DS500071-2
NM24C08
3 4 6 5
See Package Number N08E, M08A and MTC08
Pin Names
A2 VSS SDA SCL NC VCC Device Address Input Ground Serial Data I/O Serial Clock Input No Connection Power Supply
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
NC NC A2 VSS 1 2 8 7 VCC WP SCL SDA
DS500071-3
NM24C09
3 4 6 5
See Package Number N08E, M08A and MTC08
Pin Names
A2 VSS SDA SCL WP VCC NC Device Address Input Ground Serial Data I/O Serial Clock input Write Protect Power Supply No Connection
NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Ordering Information NM 24 C XX F LZ E XXX
Package
Letter
N M8 MT8 None V E Blank L LZ
Description
8-pin DIP 8-pin SOIC 8-pin TSSOP 0 to 70C -40 to +125C -40 to +85C 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V and <1A Standby Current 100KHz 400KHz 8K 8K with Write Protect CMOS Technology IIC Fairchild Non-Volatile Memory
Temp. Range
Voltage Operating Range
SCL Clock Frequency
Blank F 08 09 C
Density
Interface
24 NM
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Product Specifications Absolute Maximum Ratings
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating -65C to +150C 6.5V to -0.3V +300C 2000V min.
Operating Conditions
Ambient Operating Temperature NM24C08/09 NM24C08E/09E NM24C08V/09V Positive Power Supply NM24C08/09 NM24C08L/09L NM24C08LZ/09LZ 0C to +70C -40C to +85C -40C to +125C 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V
DC Electrical Characteristics (2.7V to 5.5V)
Symbol Parameter Test Conditions Min
ICCA ISB Active Power Supply Current Standby Current fSCL = 400 KHz fSCL = 100 KHz VIN = GND or VCC VCC = 2.7V - 5.5V VCC = 2.7V - 5.5V (L) VCC = 2.7V - 4.5V (LZ)
Limits Typ (Note 1)
0.2 10 1 0.1 0.1 0.1
Units Max
1.0 50 10 1 1 1 VCC x 0.3 VCC + 0.5 0.4 mA A A A A A V V V
ILI ILO VIL VIH VOL
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage
VIN = GND to VCC VOUT = GND to VCC -0.3 VCC x 0.7 IOL = 3 mA
Capacitance TA = +25C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
CI/O CIN
Test
Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL)
Conditions
VI/O = 0V VIN = 0V
Max
8 6
Units
pF pF
Note 1: Typical values are TA = 25C and nominal supply voltage of 5V for 4.5V-5.5V operation and at 3V for 2.7V-4.5V operation. Note 2: This parameter is periodically sampled and not 100% tested.
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Input & Output Timing Levels Output Load VCC x 0.1 to VCC x 0.9 10 ns VCC x 0.3 to VCC x 0.7 1 TTL Gate and CL = 100 pF
AC Testing Input/Output Waveforms
0.9VCC 0.1VCC 0.7VCC 0.3VCC
DS500071-4
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
fSCL TI
Parameter
SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs (Minimum VIN Pulse width) SCL Low to SDA Data Out Valid Time the Bus Must Be Free before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time - NM24C08/09 - NM24C08/09L, NM24C08/09LZ
100 KHz Min Max
100 100 0.3 4.7 4.0 4.7 4.0 4.7 20 250 1 300 4.7 300 10 15 3.5
400 KHz Min Max
400 50 0.1 1.3 0.6 1.5 0.6 0.6 20 100 0.3 300 0.6 50 10 15 0.9
Units
KHz ns s s s s s s ns ns s ns s ns ms
tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tWR (Note 3)
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the NM24C08/09 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer "Write Cycle Timing" diagram.
Bus Timing
tF tHIGH tLOW SCL tLOW tR
SDA IN
SDA OUT
;;
tSU:STA tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF tDH
tAA
DS500071-5
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Write Cycle Timing
SCL
SDA
8th BIT WORD n
ACK tWR STOP CONDITION START CONDITION
DS500071-6
Note:
The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
Typical System Configuration
VCC VCC
SDA SCL Master Transmitter/ Receiver
Note:
Slave Receiver
Slave Transmitter/ Receiver
Master Transmitter
Master Transmitter/ Receiver
DS500071-7
Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7k)
Example of 16K of Memory on 2-Wire Bus
Note: The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices. The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state. It is recommended that the total line capacitance be less than 400pF
VCC
VCC
SDA SCL
VCC VCC VCC VCC
NM24C02/03
A0 A1 A2 VSS
NM24C02/03
A0 A1 A2 VSS
NM24C04/05
A1 A2 VSS
NM24C08/09
A2 VSS
To To To VSS VSS VSS
To To To VCC VSS VSS
To To VCC VSS
To VCC
DS500071-8
Device A0
NM24C02/03 NM24C04/05 NM24C08/09 NM24C16/17 Yes No No No
Address Pins Present A1
Yes Yes No No
Memory Size A2
Yes Yes Yes No 2048 Bits 4096 Bits 8192 Bits 16,384 Bits
# of Page Blocks
1 2 4 8
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Background Information (IIC Bus)
IIC bus allows synchronous bi-directional communication between a TRANSMITTER and a RECEIVER using a Clock signal (SCL) and a Data signal (SDA). Additionally there are up to three Address signals (A2, A1 and A0) which collectively serve as "chip select signal" to a device (example EEPROM) on the IIC bus. All communication on the IIC bus must be started with a valid START condition (by a MASTER), followed by transmittal (by the MASTER) of byte(s) of information (Address/Data). For every byte of information received, the addressed RECEIVER provides a valid ACKNOWLEDGE pulse to further continue the communication unless the RECEIVER intends to discontinue the communication. Depending on the direction of transfer (Write or Read), the RECEIVER can be a SLAVE or the MASTER. A typical IIC communication concludes with a STOP condition (by the MASTER). Addressing an EEPROM memory location involves sending a command string with the following information: [DEVICE TYPE]--[DEVICE/PAGE BLOCK SELECTION]--[R/W BIT]--{acknowledge pulse}--[ARRAY ADDRESS]
Acknowledge
Acknowledge is an active LOW pulse on the SDA line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8-bits of data. The receiver provides an ACK pulse for every 8-bits of data received. This handshake mechanism is done as follows: After transmitting 8-bits of data, the transmitter releases the SDA line and waits for the ACK pulse. The addressed receiver, if present, drives the ACK pulse on the SDA line during the 9th clock and releases the SDA line back (to the transmitter). Refer Figure 3.
Array Address
Array address is an 8-bit information containing the address of a memory location to be selected within a page block of the device.
16K bit Addressing Limitation:
Standard IIC specification limits the maximum size of EEPROM memory on the bus to 16K bits. This limitation is due to the addressing protocol implemented which consists of the 8-bit Slave Address and an additional 8-bit field called Array Address. This Array Address selects 1 out of 256 locations (28=256). Since the data format of IIC specification is 8-bit wide, a total of 256 x 8 = 2048 = 2K bit now becomes addressable by this 8-bit Array Address. This 2K bit is typically referred as a "Page Block". Combining this 8-bit Array Address with the 3-bit Device/Page address (part of Slave Address) allows a maximum of 8 pages (23=8) of memory that can be addressed. Since each page is 2K bit in size, 8 x 2K bit = 16K bit is the maximum size of memory that is addressable on the Standard IIC bus. This 16Kb of memory can be in the form of a single 16Kb EEPROM device or multiple EEPROMs of varying density (in 2Kb multiples) to a maximum total of 16Kb. To address the needs of systems that require more than 16Kb on the IIC bus, a different specification called "Extended IIC Specification" is used. Please refer to NM24C32xx Datasheet for more information on Extended IIC Specification.
Slave Address
Slave Address is an 8-bit information consisting of a Device type field (4bits), Device/Page block selection field (3bits) and Read/ Write bit (1bit).
Slave Address Format
Device Type Identifier Device/Page Block Selection
1
0
1
0
A2
A1
A0
R/W
(LSB)
DS500071-9
Device Type
IIC bus is designed to support a variety of devices such as RAMs, EPROMs etc., along with EEPROMS. Hence to properly identify various devices on the IIC bus, a 4-bit "Device Type" identifier string is used. For EEPROMS, this 4-bit string is 1-0-1-0. Every IIC device on the bus internally compares this 4-bit string to its own "Device Type" string to ensure proper device selection. WORD PAGE
DEFINITIONS
8 bits (byte) of data 16 sequential byte locations starting at a 16-byte address boundary, that may be programmed during a "page write" programming cycle 2048 (2K) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2048 bits Any IIC device CONTROLLING the transfer of data (such as a microprocessor) Device being controlled (EEPROMs are always considered Slaves) Device currently SENDING data on the bus (may be either a Master or Slave). Device currently RECEIVING data on the bus (Master or Slave)
Device/Page Block Selection
When multiple devices of the same type (e.g. multiple EEPROMS) are present on the IIC bus, then the A2, A1 and A0 address information bits are also used as part of the Slave Address. Every IIC device on the bus internally compares this 3-bit string to its own physical configuration (A2, A1 and A0 pins) to ensure proper device selection. This comparison is in addition to the "Device Type" comparison. In addition to selecting an EEPROM, these 3 bits are also used to select a "page block" within the selected EEPROM. Each page block is 2Kbit (256Bytes) in size. Depending on the density, an EEPROM can contain from a minimum of 1 to a maximum of 8 page blocks (in multiples of 2) and selection of a page block within a device is by using A2, A1 and A0 bits.
PAGE BLOCK
MASTER
SLAVE
TRANSMITTER
Read/Write Bit
Last bit of the Slave Address indicates if the intended access is Read or Write. If the bit is "1," then the access is Read, whereas if the bit is "0," then the access is Write. RECEIVER
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Device Operation
The NM24C08/09 supports a bi-directional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the NM24C08/09 will be considered a slave in all applications.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
Write Protect (WP) (NM24C09 Only)
If tied to VCC, PROGRAM operations onto the upper half (upper 4Kbit) of the memory will not be executed. READ operations are possible. If tied to VSS, normal operation is enabled, READ/ WRITE over the entire memory is possible. This feature allows the user to assign the upper half of the memory as ROM which can be protected against accidental programming. When write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. This pin has an internal pull-down circuit. However, on systems where write protection is not required it is recommended that this pin is tied to VSS.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figure 1 and Figure 2 on next page.
Start Condition
All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The NM24C08/ 09 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Stop Condition
All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the NM24C08/09 to place the device in the standby power mode, except when a Write operation is being executed, in which case a second stop condition is required after tWR period, to place the device in standby mode.
Device Selection Inputs A2, A1 and A0 (as appropriate)
These inputs collectively serve as "chip select" signal to an EEPROM when multiple EEPROMs are present on the same IIC bus. Hence these inputs, if present, should be connected to VCC or VSS in a unique manner to allow proper selection of an EEPROM amongst multiple EEPROMs. During a typical addressing sequence, every EEPROM on the IIC bus compares the configuration of these inputs to the respective 3 bit "Device/Page block selection" information (part of slave address) to determine a valid selection. For e.g. if the 3 bit "Device/Page block selection" is 10-1, then the EEPROM whose "Device Selection inputs" (A2, A1 and A0) are connected to VCC-VSS-VCC respectively, is selected. Depending on the density, only appropriate number of "Device Selection inputs" are provided on an EEPROM. For every "Device selection input" that is not present on the device, the corresponding bit in the "Device/Page block selection" field is used to select a "Page Block" within the device instead of the device itself. Following table illustrates the above:
EEPROM Density
2k bit 4k bit 8k bit 16k bit
Number of Page Blocks
1 2 4 8
Device Selection Inputs Provided
A0 -- -- -- A1 A1 -- -- A2 A2 A2 --
Address Bits Selecting Page Block
None A0 A0 and A1 A0, A1 and A2
Note that even when just one EEPROM present on the IIC bus, these pins should be tied to VCC or VSS to ensure proper termination.
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Data Validity (Figure 1)
SCL
SDA
DATA STABLE DATA CHANGE
DS500071-10
Start and Stop Definition (Figure 2)
SCL
SDA START CONDITION STOP CONDITION
DS500071-11
Acknowledge Response from Receiver (Figure 3)
SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER
1
8
9
tDH
DATA OUTPUT FROM RECEIVER
START CONDITION
tAA
ACKNOWLEDGE PULSE
DS500071-12
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Acknowledge
The NM24C08/09 device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the NM24C08/09 will respond with an acknowledge after the receipt of each subsequent eight bit byte. In the read mode the NM24C08/09 slave will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected, NM24C08/09 will continue to transmit data. If an acknowledge is not detected,NM24C08/09 will terminate further data transmissions and await the stop condition to return to the standby power mode.
Refer the following table for Slave Addresses string details:
Device
NM24C08/09
A0 A1 A2 Page Blocks
P P A 4
Page Block Addresses
00, 01, 10, 11
A: Refers to a hardware configured Device Address pin. P: Refers to an internal PAGE BLOCK.
All IIC EEPROMs use an internal protocol that defines a PAGE BLOCK size of 2K bits (for Word addresses 0x00 through 0xFF). Therefore, address bits A0, A1, or A2 (if designated 'P') are used to access a PAGE BLOCK in conjunction with the Word address used to access any individual data byte. The last bit of the slave address defines whether a write or read condition is requested by the master. A '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. A simple review: After the NM24C08/09 recognizes the start condition, the devices interfaced to the IIC bus wait for a slave address to be transmitted over the SDA line. If the transmitted slave address matches an address of one of the devices, the designated slave pulls the line LOW with an acknowledge signal and awaits further transmissions.
Device Addressing
Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are those of the device type identifier. This is fixed as 1010 for all EEPROM devices.
Device Type Identifier
Device Address
1
0
1
0
A2
A1
A0
R/W
(LSB)
NM24C08/09
Page Block Address
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Write Operations
BYTE WRITE
For a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. Upon receipt of the byte address the NM24C08/09 responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the NM24C08/ 09 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the NM24C08/09 inputs are disabled, and the device will not respond to any requests from the master for the duration of tWR. Refer to Figure 4 for the address, acknowledge and data transfer sequence. Page Write is initiated in the same manner as the Byte Write operation; but instead of terminating the cycle after transmitting the first data byte, the master can further transmit up to 15 more bytes. After the receipt of each byte, NM24C08/09 will respond with an acknowledge pulse, increment the internal address counter to the next address and is ready to accept the next data. If the master should transmit more than sixteen bytes prior to generating the STOP condition, the address counter will "roll over" and previously written data will be overwritten. As with the Byte Write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host's write operation the NM24C08/09 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the NM24C08/09 is still busy with the write operation no ACK will be returned. If the NM24C08/09 has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation.
PAGE WRITE
To minimize write cycle time, NM24C08/09 offer Page Write feature, by which, up to a maximum of 16 contiguous bytes locations can be programmed all at once (instead of 16 individual byte writes). To facilitate this feature, the memory array is organized in terms of "Pages." A Page consists of 16 contiguous byte locations starting at every 16-Byte address boundary (for example, starting at array address 0x00, 0x10, 0x20 etc.). Page Write operation limits access to byte locations within a page. In other words a single Page Write operation will not cross over to locations on another page but will "roll over" to the beginning of the page whenever end of Page is reached and additional locations are a continued to be accessed. A Page Write operation can be initiated to begin at any location within a page (starting address of the Page Write operation need not be the starting address of a Page).
Write Protection (NM24C09 Only)
Programming of the upper half (upper 4Kbit) of the memory will not take place if the WP pin of the NM24C09 is connected to VCC. The NM24C09 will respond to slave and byte addresses; but if the memory accessed is write protected by the WP pin, the NM24C09 will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted.
Byte Write (Figure 4)
S T A R T S T O P
Bus Activity: Master SDA Line Bus Activity: EEPROM
SLAVE ADDRESS
WORD ADDRESS
DATA
A C K
A C K
A C K
DS500071-13
Page Write (Figure 5)
S T A R T S T O P
Bus Activity: Master SDA Line Bus Activity: EEPROM
SLAVE ADDRESS
WORD ADDRESS (n)
DATA n
DATA n + 1
DATA n + 15
A C K
A C K
A C K
A C K
A C K
DS500071-14
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Read Operations
Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read, and sequential read.
Current Address Read
Internally the NM24C08/09 contains an address counter that maintains the address of the last byte accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with R/W set to one, the NM24C08/09 issues an acknowledge and transmits the eight bit byte. The master will not acknowledge the transfer but does generate a stop condition, and therefore the NM24C08/09 discontinues transmission. Refer to Figure 6 for the sequence of address, acknowledge and data transfer.
master immediately issues another start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the NM24C08/09 and then by the eight bit byte. The master will not acknowledge the transfer but does generate the stop condition, and therefore the NM24C08/09 discontinues transmission. Refer to Figure 7 for the address, acknowledge and data transfer sequence.
Sequential Read
Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The NM24C08/09 continues to output data for each acknowledge received. The read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. After the entire memory has been read, the counter "rolls over" to the beginning of the memory. NM24C08/09 continues to output data for each acknowledge received. Refer to Figure 8 for the address, acknowledge, and data transfer sequence.
Random Read
Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition, slave address with the R/W bit set to zero and then the byte address it is to read. After the byte address acknowledge, the
Current Address Read (Figure 6)
Bus Activity: Master SDA Line Bus Activity: EEPROM S T A R T SLAVE ADDRESS 101 0 1 A C K NO A C K
DS500071-15
S T O P
DATA
Random Read (Figure 7)
Bus Activity: Master SDA Line Bus Activity: EEPROM A C K A C K A C K DATA n NO A C K S T A R T SLAVE ADDRESS WORD ADDRESS S T A R T SLAVE ADDRESS S T O P
DS500071-16
Sequential Read (Figure 8)
Bus Activity: Master SDA Line Bus Activity: EEPROM A C K
DATA n +1 DATA n +1 DATA n + 2 DATA n + x Slave Address
A C K
A C K
A C K
S T O P
NO A C K
DS500071-17
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NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197 (4.800 - 5.004)
8765
0.228 - 0.244 (5.791 - 6.198)
1234
Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 8 Max, Typ. All leads 0.04 (0.102) All lead tips
0.010 - 0.020 x 45 (0.254 - 0.508)
0.053 - 0.069 (1.346 - 1.753)
0.004 - 0.010 (0.102 - 0.254) Seating Plane
0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads
0.016 - 0.050 (0.406 - 1.270) Typ. All Leads
0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508)
8-Pin Molded Small Outline Package (M8) Package Number M08A
0.114 - 0.122 (2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ (0.65) Typ
0.246 - 0.256 (6.25 - 6.5)
0.123 - 0.128 (3.13 - 3.30)
1
4
Pin #1 IDENT
Land pattern recommendation
0.0433 Max (1.1) 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) Typ.
See detail A
0.0035 - 0.0079
0.0075 - 0.0098 (0.19 - 0.30)
0-8
Gage plane
DETAIL A Typ. Scale: 40X
0.020 - 0.028 (0.50 - 0.70) Seating plane
0.0075 - 0.0098 (0.19 - 0.25)
Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded Thin Shrink Small Outline Package (MT8) Package Number MTC08
13
NM24C08/09 Rev. G
www.fairchildsemi.com
NM24C08/09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 0.092 DIA (2.337) Pin #1 IDENT Option 1
8
+
7
6
5
0.250 - 0.005 (6.35 0.127)
0.032 0.005 (0.813 0.127) RAD Pin #1 IDENT
8
7
1 1 2 3 4
0.039 (0.991) 0.130 0.005 (3.302 0.127) Option 2 0.145 - 0.200 (3.683 - 5.080) 0.040 Typ. (1.016)
0.280 MIN (7.112) 0.300 - 0.320 (7.62 - 8.128)
0.030 MAX (0.762) 20 1
95 5 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM
0.065 (1.651)
0.125 - 0.140 (3.175 - 3.556) 90 4 Typ 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.060 (1.524)
0.020 (0.508) Min
0.045 0.015 (1.143 0.381) 0.050 (1.270)
Molded Dual-In-Line Package (N) Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
14
NM24C08/09 Rev. G
www.fairchildsemi.com

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